As data is being transmitted in a computer system (or between computer systems), it is desirable at times to be able to adjust the rate that the data is being transmitted. In the case where a buffer is used for synchronization purposes such as when the source and destination of a data transmission are running under asynchronous clock signals, the data transmission rate may be controlled by controlling the rate that data is written into or read from the buffer.
In common applications, the rate that data is written into a buffer is controlled by the source clock signal, and the rate that data is read from the buffer is controlled by the destination clock signal. Such an arrangement accommodates situations where the source and destination clock signals are asynchronous, as well as where the source and destination clock signals are of different frequencies.
In more complex applications, however, where it may take several clock cycles to process data at the destination, it may be desirable to slow down reading data from the buffer by using a rate less than the destination clock frequency or alternatively, writing data to the buffer by using a rate less than the source clock frequency in order to avoid overflow conditions at the receiving end or in the buffer.
In addition, or alternatively, where the number of clock cycles to process data varies depending upon the nature or characteristics of the data being processed, or the type of processing to be performed on the data, the rate that data is read from or written to the buffer preferably varies accordingly. Therefore, it would be useful to provide a programming means to vary the rate of reading from or writing to the buffer to accommodate such cases.